Transistor devices are utilized in numerous semiconductor constructions, including, for example, memory constructions. A transistor device will typically comprise a transistor gate adjacent a semiconductive material, and defining a channel region within the semiconductor material. The transistor device will also typically comprise a pair of source/drain regions separated from one another by the channel region.
A specialized type of transistor gate is a so-called floating gate. The term “floating” transistor gate is used to indicate that no electrical connection exists to the gate. The floating gate is charged by injecting hot electrons into the gate, and once the electrons are transferred to the gate they become trapped there.
Floating gates can be incorporated into programmable read-only memory (PROM) constructions, such as erasable PROMs (EPROMS), and electrically erasable PROMs (EEPROMS). Further, the PROMs can be incorporated into FLASH devices, such as, for example, FLASH EEPROMS. A FLASH device is so named because the contents of all of the memory's array cells can be erased simultaneously and rapidly through utilization of an electrical erase signal.
Memory arrays can be fabricated utilizing numerous transistor gates in combination with various capacitor or other circuitry constructions. Frequently, it is desired to fabricate adjacent transistor gates of the memory array close to one another to conserve semiconductor real estate. One method of fabricating transistor gates is to utilize photolithographic processing to form patterned photoresist blocks over transistor gate material. Subsequently, a pattern is transferred from the blocks to the underlying transistor gate material to form transistor gate structures. A minimal spacing between adjacent patterned photoresist blocks is limited by various parameters involved in a photolithographic process. For instance, the wavelength of light utilized in photolithographic processing can limit a minimum spacing between adjacent patterned features due to interference effects which can occur if a minimal spacing between adjacent features is not maintained.
It would be desirable to develop methodology by which a spacing between adjacent transistor gates can be reduced to less than a minimum feature size achievable by photolithographic processing. It is recognized that the minimum feature size achievable by photolithographic processing is continually decreasing due to advances made in semiconductor processing methodologies. However, at any time there is a minimum feature size associated with any particular photolithographic process. It would be desirable to develop a method which can reduce the minimum feature size beyond that achieved by a particular photolithographic process at the time that the process is utilized for fabrication of semiconductor circuitry.